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16 V Rail-to-Rail, Zero-Drift, Precision Instrumentation Amplifier AD8230
FEATURES
OFFSET VOLTAGE (V RTI)
2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -50
Resistor programmable gain range: 101 to 1000 Supply voltage range: 4 V to 8 V, +8 V to +16 V Rail-to-rail input and output Maintains performance over -40C to +125C
EXCELLENT AC AND DC PERFORMANCE
110 dB minimum CMR @ 60 Hz, G = 10 to 1000 10 V max offset voltage (RTI, 5 V) 50 nV/C max offset drift 20 ppm max gain nonlinearity
-30
-10
10
30
50
70
90
110
130
150
APPLICATIONS
Pressure measurements Temperature measurements Strain measurements Automotive diagnostics
TEMPERATURE (C)
Figure 1. Relative Offset Voltage vs. Temperature
+5V -5V 0.1F 0.1F
2
GENERAL DESCRIPTION
The AD8230 is a low drift, differential sampling, precision instrumentation amplifier. Auto-zeroing reduces offset voltage drift to less than 50 nV/C. The AD8230 is well-suited for thermocouple and bridge transducer applications. The AD8230's high CMR of 110 dB (min) rejects line noise in measurements where the sensor is far from the instrumentation. The 16 V rail-to-rail, common-mode input range is useful for noisy environments where ground potentials vary by several volts. Low frequency noise is kept to a minimal 3 V p-p making the AD8230 perfect for applications requiring the utmost dc precision. Moreover, the AD8230 maintains its high performance over the extended industrial temperature range of -40C to +125C. Two external resistors are used to program the gain. By using matched external resistors, the gain stability of the AD8230 is much higher than instrumentation amplifiers that use a single resistor to set the gain. In addition to allowing users to program the gain between 101 and 1000, users may adjust the output offset voltage.
4
1
TYPE K THERMOCOUPLE
5
AD8230
7 6 3
8
VOUT
34.8k 284
05063-002
Figure 2. Thermocouple Measurement
The AD8230 is versatile yet simple to use. Its auto-zeroing topology significantly minimizes the input and output transients typical of commutating or chopper instrumentation amplifiers. The AD8230 operates on 4 V to 8 V (+8 V to +16 V) supplies and is available in an 8-lead SOIC.
1
The AD8230 can be programmed for a gain as low as 2, but the maximum input voltage is limited to approximately 750 mV.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
05063-107
AD8230 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ...................................................................... 10 Setting the Gain .......................................................................... 10 Level-Shifting the Output.......................................................... 11 Source Impedance and Input Settling Time ........................... 11 Input Voltage Range ................................................................... 11 Input Protection ......................................................................... 11 Power Supply Bypassing ............................................................ 11 Power Supply Bypassing for Multiple Channel Systems ....... 11 Layout .......................................................................................... 12 Applications ................................................................................ 12 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13
REVISION HISTORY
10/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8230 SPECIFICATIONS
VS = 5 V, VREF = 0 V, RF = 100 k, RG = 1 k (@ TA = 25C, G = 202, RL = 10 k, unless otherwise noted). Table 1.
Parameter VOLTAGE OFFSET RTI Offset, VOSI Offset Drift COMMON-MODE REJECTION (CMR) CMR to 60 Hz with 1 k Source Imbalance VOLTAGE OFFSET RTI vs. SUPPLY (PSR) G=2 G = 202 GAIN Gain Range Gain Error G=2 G = 10 G = 100 G = 1000 Gain Nonlinearity INPUT Input Common-Mode Operating Voltage Range Over Temperature Input Differential Operating Voltage Range Average Input Offset Current2 OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT Voltage Range NOISE Voltage Noise Density, 1 kHz, RTI Voltage Noise SLEW RATE INTERNAL SAMPLE RATE POWER SUPPLY Operating Range (Dual Supplies) Operating Range (Single Supply) Quiescent Current TEMPERATURE RANGE Specified Performance Conditions V+IN = V-IN = 0 V V+IN = V-IN = 0 V, TA = -40C to +125C VCM = -5 V to +5 V 110 120 120 G = 2(1 + RF/RG) 101 0.01 0.01 0.01 0.02 20 -VS -VS 750 33 -VS + 0.1 -VS + 0.1 15 -1 VIN+, VIN-, VREF = 0 f = 0.1 Hz to 10 Hz VIN = 500 mV, G = 10 240 3 2 6 4 +8 T = -40C to +125C -40 2.7 8 +16 3.5 +125 +1 +VS - 0.2 +VS - 0.2 +VS +VS 1000 V/V % % % % ppm V V mV pA V V mA V nV/Hz V p-p V/s kHz V V mA C 120 120 140 Min Typ Max 10 50 Unit V nV/C
dB dB dB
T = -40C to +125C VCM = 0V
T = -40C to +125C
1
The AD8230 can operate as low as G = 2. However, since the differential input range is limited to approximately 750 mV, the AD8230 configured at G < 10 does not make use of the full output voltage range. 2 Differential source resistance less than 10 k does not result in voltage offset due to input bias current or mismatched series resistors.
Rev. 0 | Page 3 of 16
AD8230
VS = 8 V, VREF = 0 V, RF = 100 k, RG = 1 k (@ TA = 25C, G = 202, RL = 10 k, unless otherwise noted). Table 2.
Parameter VOLTAGE OFFSET RTI Offset, VOSI Offset Drift COMMON-MODE REJECTION (CMR) CMR to 60 Hz with 1 k Source Imbalance VOLTAGE OFFSET RTI vs. SUPPLY (PSR) G=2 G = 202 GAIN Gain Range Gain Error G=2 G = 10 G = 100 G = 1000 Gain Nonlinearity INPUT Input Common-Mode Operating Voltage Range Over Temperature Input Differential Operating Voltage Range Average Input Offset Current2 OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT Voltage Range NOISE Voltage Noise Density, 1 kHz, RTI Voltage Noise SLEW RATE INTERNAL SAMPLE RATE POWER SUPPLY Operating Range (Dual Supplies) Operating Range (Single Supply) Quiescent Current TEMPERATURE RANGE Specified Performance Conditions V+IN = V-IN = 0 V V+IN = V-IN = 0 V, T = -40C to +125C VCM = -8 V to +8 V 110 120 120 G = 2(1 + RF/RG) 101 0.01 0.01 0.01 0.02 20 -VS -VS 750 33 -VS + 0.1 -VS + 0.1 15 -1 VIN+, VIN-, VREF = 0 f = 0.1 Hz to 10 Hz VIN = 500 mV, G = 10 240 3 2 6 4 +8 T = -40C to +125C -40 3.2 8 +16 4 +125 +1 +VS - 0.2 +VS - 0.4 +VS +VS 1000 V/V % % % % ppm V V mV pA V V mA V nV/Hz V p-p V/s kHz V V mA C 120 120 140 Min Typ Max 20 50 Unit V nV/C
dB dB dB
T = -40C to +125C VCM = 0V
T = -40C to +125C
1
The AD8230 can operate as low as G = 2. However, since the differential input range is limited to approximately 750 mV, the AD8230 configured at G < 10 does not make use of the full output voltage range. 2 Differential source resistance less than 10 k does not result in voltage offset due to input bias current or mismatched series resistors.
Rev. 0 | Page 4 of 16
AD8230 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Internal Power Dissipation Output Short-Circuit Current Input Voltage (Common-Mode) Differential Input Voltage Storage Temperature Operational Temperature Range Rating 8 V, +16 V 304 mW 20 mA VS VS -65C to +150C -40C to +125C
CONNECTION DIAGRAM
-VS 1 +VS 2 VREF1 3 +IN 4
8 VOUT 7 RG 6 VREF2 5 -IN
05063-001
AD8230
TOP VIEW (Not to Scale)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Specification is for device in free air: SOIC: JA (4-layer JEDEC board) = 121C/W.
Figure 3.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 16
AD8230 TYPICAL PERFORMANCE CHARACTERISTICS
TOTAL NUMBER OF SAMPLES = 2839 FROM 3 LOTS 500
OFFSET VOLTAGE (V RTI)
20 NORMALIZED FOR VCM = 0V 15 10 5 0 -5 -10
05063-007
400
SAMPLES
300
200
100
05063-100
-15 -20 -6 -4 -2 0 2 4 6 COMMON-MODE VOLTAGE (V)
0 -9 -6 -3 0 3 6 9 OFFSET VOLTAGE (V RTI)
Figure 4. Offset Voltage (RTI) Distribution at 5 V, CM = 0 V, TA = +25C
40 35
Figure 7. Offset Voltage (RTI) vs. Common-Mode Voltage, VS = 5 V
20 NORMALIZED FOR VCM = 0V 15
OFFSET VOLTAGE (V RTI)
TOTAL NUMBER OF SAMPLES = 300 FROM 3 LOTS
30 25
10 5 0 -5 -10
05063-008
SAMPLES
20 15 10
05063-108
5 0 -50
-15 -20 -10
-30
-10
10
30
50
-8
-6
-4
-2
0
2
4
6
8
10
OFFSET VOLTAGE DRIFT (nV/C)
COMMON-MODE VOLTAGE (V)
Figure 5. Offset Voltage (RTI) Drift Distribution
0 -2 -4
Figure 8. Offset Voltage (RTI) vs. Common-Mode Voltage, VS = 8 V
0 -1
OFFSET VOLTAGE (V RTI)
-6 -8 -10 -12 -14 -16 -18 -20 -50
OFFSET VOLTAGE (V)
VS = 5V
-2 -3 -4 -5 -6
05063-009
VS = 8V
5V SUPPLY
05063-005
-7 -8 0 1 2
8V SUPPLY
-30
-10
10
30
50
70
90
110
130
150
3
4
5
6
TEMPERATURE (C)
SOURCE IMPEDANCE (k)
Figure 6. Offset Voltage (RTI) vs. Temperature
Figure 9. Offset Voltage (RTI) vs. Source Impedance, 1 F Across Input Pins
Rev. 0 | Page 6 of 16
AD8230
40 NORMALIZED FOR VREF = 0V 30
OFFSET VOLTAGE (V RTI) CLOCK FREQUENCY (Hz)
6.6k 6.4k 8V 6.2k 6.0k 5V 6.8k
20 10 0 -10 -20
05063-010
5.8k 5.6k 5.4k -50
-40 -1.5
-1.0
-0.5
0 VREF (V)
0.5
1.0
1.5
-30
-10
10
30
50
70
90
110
130
TEMPERATURE (C)
Figure 10. Offset Voltage (RTI) vs. Reference Voltage
130 CMR WITH NO SOURCE IMBALANCE 120
AVERAGE INPUT BIAS CURRENT (A)
0.8
Figure 13. Clock Frequency vs. Temperature
1.0 +85C +125C 0.6 0.4 0.2 0 -0.2 -0.4 0C -0.6 -0.8 -1.0 -6 -4 -2 0 2 4 6 COMMON-MODE VOLTAGE (V) +25C
05063-020
110 100
-40C
CMR (dB)
90 80 70 60
05063-011
CMR WITH 1k SOURCE IMBALANCE
50 40 10 100 FREQUENCY (Hz) 1k 10k
Figure 11. Common-Mode Rejection vs. Frequency
Figure 14. Average Input Bias Current vs. Common-Mode Voltage -40C, +25C, +85C, +125C
3.5 3.4 8V 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -50
05063-018
130 128 126 124
CMR (dB)
122 120 118 116 114 112 110 0 2 4 6 8 10 12 SOURCE IMPEDANCE (k)
05063-012
5V SUPPLY
POSITIVE SUPPLY CURRENT (mA)
5V
8V SUPPLY
0
50 TEMPERATURE (C)
100
150
Figure 12. Common-Mode Rejection vs. Source Impedance, 1.1 F Across Input Pins
Figure 15. Supply Current vs. Temperature
Rev. 0 | Page 7 of 16
05063-013
-30
AD8230
90 80 70 60
90 80 70 60
GAIN (dB)
GAIN (dB)
50 40 30 20 10
05063-014
50 40 30 20 10 0 -10 10 100 1k FREQUENCY (Hz) 10k
05063-016
0 -10 10 100 1k FREQUENCY (Hz) 10k
100k
100k
Figure 16. Gain vs. Frequency, G = 2
90 80 70 60
GAIN (dB) GAIN (dB)
Figure 19. Gain vs. Frequency, G = 100
90 80 70 60 50 40 30 20 10
05063-015
50 40 30 20 10 0 -10 10 100 1k FREQUENCY (Hz) 10k
0 -10 10 100 1k FREQUENCY (Hz) 10k
100k
100k
Figure 17. Gain vs. Frequency, G = 10
40 G = +20 30 20
NONLINEARITY (ppm)
Figure 20. Gain vs. Frequency, G = 1000
0.010 0.008 0.006 0.004
10 0 -10 -20
GAIN ERROR (%)
0.002 0 -0.002 -0.004 -0.006
05063-019
-0.008 -0.010 0 5 10 SOURCE IMPEDANCE (k) 15 20
-40 -5
-4
-3
-2
-1
0 VOUT (V)
1
2
3
4
5
Figure 18. Gain Nonlinearity, G = 20
Figure 21. Gain Error vs. Differential Source Impedance
Rev. 0 | Page 8 of 16
05063-036
-30
05063-017
AD8230
0.35 0.30 0.25
PSR (dB)
140 120
G = +100
100 G = +1000
0.20
80 60
V/ Hz
0.15 0.10 0.05 0 1 10 100 1k 10k FREQUENCY (Hz)
G = +10 G = +2
40
05063-024
100k
0 0.1
1 FREQUENCY (kHz)
10
Figure 22. Voltage Noise Spectral Density
3.90
Figure 25. Negative PSR vs. Frequency, RTI
10 8 VS = 8V -40C
POSITIVE SUPPLY CURRENT (mA)
3.70
6
OUTPUT VOLTAGE SWING (V)
-40C 4 2 +125C 0 -2 -4 -6 -8 -10 0 2 4 6 8 VS = 8V VS = 5V +125C VS = 5V
3.50 3.30
+125C
+25C
+25C +25C
3.10
2.90
-40C +125C -40C 10
+25C
05063-109
2.50 2V/DIV -50 -30
05063-102
2.70
-10
10
30
50
70
90
1s/DIV 110 130
12
TEMPERATURE (C)
OUTPUT CURRENT (mA)
Figure 23. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 100)
Figure 26. Output Voltage Swing vs. Output Current, -40C, +25C, +85C, +125C
160 140 120 100
PSR (dB)
G = +1000
G = +100 80 G = +2 60 40
G = +10
0 0.1
1 FREQUENCY (kHz)
10
Figure 24. Positive PSR vs. Frequency, RTI
05063-034
20
Rev. 0 | Page 9 of 16
05063-035
20
AD8230 THEORY OF OPERATION
Auto-zeroing is a dynamic offset and drift cancellation technique that reduces input referred voltage offset to the V level and voltage offset drift to the nV/C level. A further advantage of dynamic offset cancellation is the reduction of low frequency noise, in particular the 1/f component. The AD8230 is an instrumentation amplifier that uses an auto-zeroing topology and combines it with high commonmode signal rejection. The internal signal path consists of an active differential sample-and-hold stage (preamp) followed by a differential amplifier (gain amp). Both amplifiers implement auto-zeroing to minimize offset and drift. A fully differential topology increases the immunity of the signals to parasitic noise and temperature effects. Amplifier gain is set by two external resistors for convenient TC matching. The signal sampling rate is controlled by an on-chip, 6 kHz oscillator and logic to derive the required nonoverlapping clock phases. For simplification of the functional description, two sequential clock phases, A and B, are used to distinguish the order of internal operation, as depicted in Figure 27 and Figure 28, respectively.
PREAMP -VS V+IN VDIFF +VCM V-IN CSAMPLE - + CHOLD -VS VREF RG RF
05063-103
In Phase B, the differential signal is transferred to the hold capacitors refreshing the value stored on CHOLD. The output of the preamplifier is held at a common-mode voltage determined by the reference potential, VREF. In this manner, the AD8230 is able to condition the difference signal and set the output voltage level. The gain amplifier conditions the updated signal stored on the hold capacitors, CHOLD.
SETTING THE GAIN
Two external resistors set the gain of the AD8230. The gain is expressed in the following function:
Gain = 2(1 + RF ) RG
+VS -VS 10F 0.1F 0.1F
4 2 1
10F
AD8230
5
RG
7
8
VOUT
VREF2 VREF1
6 3
RF RG
GAIN AMP
CHOLD + - VOUT
Figure 29. Gain Setting
Table 4. Gains Using Standard 1% Resistors
Gain 2 10 50 100 200 500 1000 RF 0 (short) 8.06 k 12.1 k 9.76 k 10 k 49.9 k 100 k RG None 2 k 499 200 100 200 200 Actual Gain 2 10 50.5 99.6 202 501 1002
Figure 27. Phase A of the Sampling Phase
During Phase A, the sampling capacitors are connected to the inputs. The input signal's difference voltage, VDIFF, is stored across the sampling capacitors, CSAMPLE. Since the sampling capacitors only retain the difference voltage, the common-mode voltage is rejected. During this period, the gain amplifier is not connected to the preamplifier so its output remains at the level set by the previously sampled input signal held on CHOLD, as shown in Figure 27.
PREAMP -VS V+IN VDIFF +VCM V-IN CSAMPLE - + CHOLD -VS VREF RG RF
05063-104
GAIN AMP
Figure 29 and Table 4 provide an example of some gain settings. As Table 4 shows, the AD8230 accepts a wide range of resistor values. Since the instrumentation amplifier has finite driving capability, make sure that the output load in parallel with the sum of the gain setting resistors is greater than 2 k. RL||(RF + RG) > 2 k
CHOLD + - VOUT
Figure 28. Phase B of the Sampling Phase
Offset voltage drift at high temperature can be minimized by keeping the value of the feedback resistor, RF, small. This is due to the junction leakage current on the RG pin, Pin 7. The effect of the gain setting resistor on offset voltage drift is shown in Figure 30. In addition, experience has shown that wire-wound resistors in the gain feedback loop may degrade the offset voltage performance.
Rev. 0 | Page 10 of 16
05063-030
AD8230
0
INPUT VOLTAGE RANGE
The input common-mode range of the AD8230 is rail to rail. However, the differential input voltage range is limited to, approximately, 750 mV. The AD8230 does not phase invert when its inputs are overdriven.
-1
OFFSET VOLTAGE (V RTI)
-2
INPUT PROTECTION
-3 RF = 100k, RG = 1k
-4 RF = 10k, RG = 100 0 50 TEMPERATURE (C) 100 150
05063-110
-5 -50
The input voltage is limited to within one diode drop beyond the supply rails by the internal ESD protection diodes. Resistors and low leakage diodes may be used to limit excessive, external voltage and current from damaging the inputs, as shown in Figure 32. Figure 34 shows an overvoltage protection circuit between the thermocouple and the AD8230.
+VS BAV199 0.1F +VS -VS -VS
Figure 30. Effect of Feedback Resistor on Offset Voltage Drift
LEVEL-SHIFTING THE OUTPUT
A reference voltage, as shown in Figure 31, can be used to levelshift the output 1 V from midsupply. Otherwise, it is nominally tied to midsupply. The voltage source used to level-shift the output should have a low output impedance to avoid contributing to gain error. In addition, it should be able to source and sink current. To minimize offset voltage, the VREF pins should be connected either to the local ground or to a reference voltage source that is connected to the local ground.
+VS -VS 0.1F 0.1F
2 4 1
0.1F
2 4
2.49k 2.49k
5
1
AD8230
7 6 3
8
VOUT
19.1k 200
05063-037
+VS -VS BAV199
Figure 32. Overvoltage Input Protection
POWER SUPPLY BYPASSING
A regulated dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins may adversely affect performance. Bypass capacitors should be used to decouple the amplifier. The AD8230 has internal clocked circuitry that requires adequate supply bypassing. A 0.1 F capacitor should be placed as close to each supply pin as possible. As shown in Figure 29, a 10 F tantalum capacitor may be used further away from the part.
AD8230
5 6 3 7
8
VOUT
RF RG
05063-031
VLEVEL-SHIFT =
(+VS + -VS) 1V 2
Figure 31. Level-Shifting the Output
SOURCE IMPEDANCE AND INPUT SETTLING TIME
The input stage of the AD8230 consists of two actively driven, differential switched capacitors, as described in Figure 27 and Figure 28. Differential input signals are sampled on CSAMPLE such that the associated parasitic capacitances, 70 pF, are balanced between the inputs to achieve high common-mode rejection. On each sample period (approximately 85 s), these parasitic capacitances must be recharged to the common-mode voltage by the signal source impedance (10 k max).
POWER SUPPLY BYPASSING FOR MULTIPLE CHANNEL SYSTEMS
The best way to prevent clock interference in multichannel systems is to lay out the PCB with a star node for the positive supply and a star node for the negative supply. Each AD8230 has a pair of traces leading to the star nodes. Using such a technique, crosstalk between clocks is minimized. If laying out star nodes is unfeasible, then use thick traces to minimize parasitic inductance and decouple frequently along the power supply traces. Examples are shown in Figure 33. Care and forethought go a long way in maximizing performance.
Rev. 0 | Page 11 of 16
AD8230
-VS +VS 10F 10F 0.1F
1 2
1F 0.1F
8 7 6 5 1 2
1F
1F 0.1F
1F 0.1F
8 7 6 5 1 2
0.1F
8 7 6 5 1 2
-VS +VS
-VS +VS
8 7 6 5
1 2
-VS +VS
-VS +VS
-VS +VS
8 7 6 5
0.1F
3 4
0.1F
3 4
0.1F
3 4
0.1F
3 4
0.1F
3 4
AD8230
AD8230
STAR -VS
AD8230
AD8230
AD8230
10F STAR +VS 10F 0.1F
1 2
0.1F
8 7 6 5 1 2
0.1F
8 7 6 5 1 2
0.1F
8 7 6 5 1 2
-VS +VS
-VS +VS
-VS +VS
-VS +VS
8 7 6 5
4
4
4
4
AD8230
AD8230
AD8230
AD8230
Figure 33. Use Star Nodes for +VS and -VS or Use Thick Traces and Decouple Frequently Along the Supply Lines
LAYOUT
The AD8230 has two reference pins: VREF1 and VREF2. VREF1 draws current to set the internal voltage references. In contrast, VREF2 does not draw current. It sets the common mode of the output signal. As such, VREF1 and VREF2 should be star-connected to ground (or to a reference voltage). In addition, to maximize CMR, the trace between VREF2 and the gain resistor, RG, should be kept short.
thermocouple connection is broken. Well-matched 1% 4.99 k resistors are used in the RFI filter. It is good practice to match the source impedances to ensure high CMR. The circuit is configured for a gain of 193, which provides an overall temperature sensitivity of 10 mV/C.
+VS -VS 0.1F +VS 0.1F
2 4
APPLICATIONS
BAV199 +VS -VS +VS 100M TYPE J THERMOCOUPLE 1nF
4
+VS -VS
1
350
350
5
AD8230
7 6 3
4k
8
VOUT 1F
0.1F
2 1
0.1F
350
350
102k 1k
4.99k 4.99k 100M -VS 1nF
1F
5
AD8230
7 6 3
8
VOUT
-VS
19.1k 200
Figure 35. Bridge Measurement with Filtered Output
+VS -VS BAV199
Figure 34. Type J Thermocouple with Overvoltage Protection and RFI Filter
The AD8230 may be used in thermocouple applications, as shown in Figure 2 and Figure 34. Figure 34 is an example of such a circuit for use in an industrial environment. It has voltage overload protection (see the Input Protection section for more information) and an RFI filter in front. The matched 100 M resistors serve to provide input bias current to the input transistors and also serve as an indicator as to when the
Measuring load cells in industrial environments can be a challenge. Often, the load cell is located some distance away from the instrumentation amplifier. The common-mode potential can be several volts, exceeding the common-mode input range of many 5 V auto-zero instrumentation amplifiers. Fortunately, the AD8230's wide common-mode input voltage range spans 16 V, relieving designers of having to worry about the common-mode range.
05063-032
Rev. 0 | Page 12 of 16
05063-033
05063-106
0.1F
3
0.1F
3
0.1F
3
0.1F
3
AD8230 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5 4
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 36. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model AD8230YRZ1 AD8230YRZ-REEL1 AD8230YRZ-REEL71 AD8230-EVAL Temperature Range -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOIC 8-Lead SOIC, 13" Tape and Reel 8-Lead SOIC, 7" Tape and Reel Evaluation Board Package Option R-8 R-8 R-8
1
Z = Pb-free part.
Rev. 0 | Page 13 of 16
AD8230 NOTES
Rev. 0 | Page 14 of 16
AD8230 NOTES
Rev. 0 | Page 15 of 16
AD8230 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05063-0-10/04(0)
Rev. 0 | Page 16 of 16
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